General Description: How do I read in the EDIF file from CORE Generator core without having LeonardoSpectrum optimize the EDIF file?
The "read_coregen" command is used to read the EDIF netlist generated by the Xilinx CORE Generator tool. The EDIF netlist read is used for timing analysis, and the core itself is not altered during optimization.
Instead of treating the CORE Generator component as a black box without any timing information, "read_coregen" enables LeonardoSpectrum to see the timing through the CORE Generator module. When the EDIF netlist for the design is then written, the contents of core will not be written out. The actual content of the core is merged by the Xilinx software during the translate phase.
Some cores that CORE Generator produces are in the 'NGC' format (also XST produces NGC exclusively). Run the ngc2edif tool on the NGC file to produce a ".ndf" file (EDIF format).
Example flow for Virtex-II:
When you generate the core from CORE Generator, you are given the following files:
core_module.vho - VHDL component and instantiation templates (for VHDL flow) core_module.veo - Verilog module and instantiation templates (for Verilog flow) core_module.edn - COREGen file (core content in EDIF format, module name is core_module)
Here is a sample of a script that will read in a CORE Generator core:
# load the library load_lib xcv2 #read the coregen netlist read_coregen coremodule.edn #read the top level read top.vhd optimize -ta xcv2 #area report report_area -c # timing analysis report_delay -longest -through Q_dup0(0) auto_write spectrum.edf