General Description: When passing the CLKDV_DIVIDE attribute onto a DCM in a Virtex-II design, Synplify issues the following error:
"@E:"I:\applications\synplify\143746\dcm_startup.vhd":89:58:89:61|Compiler Error - Please check end of log for more information."
However, no further information is reported from Synplify.
The problem is that the CLKDV_DIVIDE attribute takes on the type "real" in VHDL, which Synplify cannot process. Furthermore, the attribute cannot be passed via the "xc_props" attribute. (Please see (Xilinx Answer 12923) for more information.)
To work around this problem, pass the attribute as a string type instead of a real type:
attribute CLK_DIVIDE : string; attribute CLK_DIVIDE of u1 : label is "8.0";
Another work-around to this problem is to pass the attribute through the UCF: