UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 13168

7.0 SYNPLIFY - When passing the CLKDV_DIVIDE DCM/Virtex-II attribute, Synplify reports an error without any further information

Description

Keywords: DCM, Virtex-II, CLKDV_DIVIDE, Synplify, Synplicity, real, attribute

Urgency: Standard

General Description:
When passing the CLKDV_DIVIDE attribute onto a DCM in a Virtex-II design, Synplify issues the following error:

"@E:"I:\applications\synplify\143746\dcm_startup.vhd":89:58:89:61|Compiler Error - Please check end of log for more information."

However, no further information is reported from Synplify.

Solution

The problem is that the CLKDV_DIVIDE attribute takes on the type "real" in VHDL, which Synplify cannot process. Furthermore, the attribute cannot be passed via the "xc_props" attribute. (Please see (Xilinx Answer 12923) for more information.)

To work around this problem, pass the attribute as a string type instead of a real type:

attribute CLK_DIVIDE : string;
attribute CLK_DIVIDE of u1 : label is "8.0";

Another work-around to this problem is to pass the attribute through the UCF:

INST dcm/instance CLKDV_DIVIDE=8;
AR# 13168
Date Created 11/13/2001
Last Updated 04/23/2007
Status Archive
Type General Article