AR# 13182


6.1i XST - Known Issues for the MULT18X18S (embedded Virtex-II multiplier)


Keywords: Virtex, VHDL, Verilog, XST, multiplier, MULT_STYLE, register, attribute, global, signal, 18x18, multiplier, infer, synchronous, MULT18X18, report

Urgency: Standard

General Description:
This answer record presents Known Issues for the MULT18X18S component. If the solutions provided below do not work, please open a Web Case at:



When I attach the "MULT_STYLE" attribute to a signal that represents the product of a multiplication, the attribute is ignored if the signal is registered.

To work around this problem, use the attribute as a global setting.

For more information, see the 5.1i Constraints Guide at:

NOTE: This problem is fixed in the 6.1i software release.


HDL code in the Synthesis and Simulation Design Guide that infers a MULT18X18S does not work when XST is used.

XST cannot currently infer the synchronous block multiplier in Virtex-II devices.

This problem is fixed in the latest 5.1i Service Pack, available at:
The first service pack containing the fix is 5.1i Service Pack 2.

Another way to work around the problem is to instantiate the primitive. Instantiation templates are available in the current version of the Libraries Guide at:


XST fails to infer MULT18X18S when the output is registered multiple times.

If possible, do not register the multiplier output multiple times.


When I perform the multiplication of an array in Verilog, XST infers too many MULT18X18 multipliers.

For example:
reg signed [17:0] InA [5:0];
reg signed [17:0] InB [5:0];
reg signed [35:0] O [5:0];

always @ (posedge Clk)
O [0] <= InA [0] * InB [0];
O [1] <= InA [1] * InB [1];
O [2] <= InA [2] * InB [2];
O [3] <= InA [3] * InB [3];
O [4] <= InA [4] * InB [4];
O [5] <= InA [5] * InB [5];


To work around this problem, do not perform multiplication on arrays.

For example:
reg signed [17:0] InA0, InA1, InA2, InA3, InA4, InA5;
reg signed [17:0] InB0, InB1, InB2, InB3, InB4, InB5;
reg signed [35:0] O0, O1, O2, O3, O4, O5;

always @ (posedge Clk)
O0 <= InA0 * InB0;
O1 <= InA1 * InB1;
O2 <= InA2 * InB2;
O3 <= InA3 * InB3;
O4 <= InA4 * InB4;
O5 <= InA5 * InB5;

This problem was fixed in the 5.2i software release.


XST reports more MULT18X18 blocks than are listed in the Virtex-II Pro data sheet and in the MAP and PAR reports.

This is an XST reporting error.

Please refer to the data sheets for the correct number of MULT18X18 components per device:

NOTE: This problem is fixed in the 6.1i software release.
AR# 13182
Date 03/05/2006
Status Archive
Type General Article
People Also Viewed