We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 13199

7.1i Project Navigator - Hierarchical (multi-level) testbenches fail during the VSIM step of ModelSim simulation


Keywords: ModelSim, VSIM, Project Navigator, testbench, testbenches, hierarchy, dependency, multi, level, ISE

My project, which includes multiple HDL files and hierarchical testbench files, fails in VSIM if the following are true:
- The top level of the testbench is associated with the top level of the HDL design
- The other testbench files are sub-entities of the top-level testbench and are not directly associated with the top-level HDL. As a result, the "compile" command for lower level testbench files is not added to the DO file for ModelSim.

For example, suppose a testbench has the following file hierarchy:
---> helper1
---> helper2

In this example, ISE places only the "main_testbench" under the module that is tested, and does not know where to place "helper1" and "helper2". Consequently, the ModelSim DO file only includes a compile command for "main_testbench" and not "helper1" and "helper2".


The hierarchical testbenches fail during the ModelSim VSIM step because the lower-level testbenches are never compiled. Because Project Navigator checks for file dependency based upon the top-level HDL file and does not check the testbench entities, lower-level testbenches are not added to the compile list that is passed to ModelSim. One way to work around this issue is to place the complete testbench into one file.

In the above example, all the contents of "helper1" and "helper2" should be cut and pasted into main_testbench.

You can run the testbench successfully if all lower-level testbench files are added and compiled from within ModelSim. You can also manually edit the DO file and add the lower-level testbench files for compilation before the actual testbench is simulated. In the above example, the following lines should automatically appear in your DO file:

vcom -just e -93 -explicit main_testbench.vhd
vcom -skip e -93 -explicit main_testbench.vhd

The following lines should then be added before the "vsim" statement:

vcom -just e -93 -explicit helper1.vhd
vcom -skip e -93 -explicit helper1.vhd
vcom -just e -93 -explicit helper2.vhd
vcom -skip e -93 -explicit helper2.vhd

Hierarchical test bench simulations should work correctly in ISE 8.1i.
AR# 13199
Date 12/11/2006
Status Archive
Type General Article