General Description: I am performing a schematic flow using XST-Verilog. During the conversion from schematics to Verilog, a duplication of module declarations occurs, with different schematics using the same component. During synthesis, the following error message is reported:
"ERROR:XST:1068 - <module_name>.vf Line x. Duplicate declarations of module <module_name>"
To work around this problem, open the .vf files that are created and edit them manually, changing the duplicate module names to a name that has not been used yet. (For example, add an "A" to end of the module name.)
Alternately, you may remove the module declarations from all but one file.