2. Support
  3. AR# 1323: FPGA Express: What Xilinx software is needed if FPGA Express is the design entry tool
  4. AR# 13236: 4.1i XST - XST changes internal signals declared as [0:N] into [N:0] format

AR# 13236

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4.1i XST - XST changes internal signals declared as [0:N] into [N:0] format

Description

Keywords: internal, signal, XST, VHDL, Verilog, MSB, LSB, Big, Little, Endian

Urgency: Standard

General Description:
If internal signals are declared in a Little Endian-type format [0:N], XST will reverse the order to a Big Endian-type format [N:0]. This can cause problems with monitoring the proper signals when a back-annotated simulation is performed.

Solution

The only way to work around this problem is to name all of the signals in a Big Endian [N:0] format.

This problem has been fixed with the release of software version 5.1i.
AR# 13236
Date 08/06/2003
Status Archive
Type General Article
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