General Description: Several cases have been seen where poor routing results were found to be caused by the use of module boundaries that did not coincide with tile (CLB) boundaries. It was found that PAR was defining the allowable routing area by snapping to the closest tile boundary outside the module boundary.
The results is that adjacent modules can have overlapping router resource utilization, which leads to conflicts during final assembly.
To avoid this problem, always define module boundaries so that they coincide with tile (CLB) boundaries. To do this, always define the module boundary to start (lower left) on an even component site and end on an odd site.