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  1. Xilinx - All Programmable
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  3. AR# 13261: *Obsolete * 4.1i BitGen - "SRVAL_B" and "INIT_B" on BRAMs are programmed incorrectly

AR# 13261

*Obsolete * 4.1i BitGen - "SRVAL_B" and "INIT_B" on BRAMs are programmed incorrectly

Description

Keywords: Virtex-II, BRAM, set/reset, set, reset, init, BitGen

Urgency: Standard

General Description:
The SRVAL_B (set/reset state) and INIT_B (initialization state) values for the block RAM are set to "1" if the output bit to program is greater than the width of the block RAM. Currently, the code for programming the SRVAL_B and INIT_B values looks at the configuration for Port A instead of Port B. If the width of Port A is less than the width of Port B, part of the SRVAL_B and INIT_B values will be lost.

Solution

This problem is fixed in the latest 4.1i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates.
The first service pack containing the fix is 4.1i Service Pack 3.
AR# 13261
Date 09/26/2005
Status Archive
Type ??????