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AR# 13288

4.2i Foundation - How do the simulator options affect the back-annotated netlist?


Keywords: Foundation, Aldec, Classic, simulation, options, VHDL, netlist, time_sim, NGD2VHDL, NGD2VER, design, back-annotated

Urgency: Low

General Description:
I am using the Foundation Aldec GUI. If I select Design -> Options -> Simulation, I can choose one of many different simulation tools. How do the various simulator options affect the back-annotated netlist?


Depending upon the simulation tool selected, the simulation options listed under the "Edit Options" button are automatically set.

For example, if "Verilog-XL" is selected, the "Include 'uselib directive in Verilog file" option is automatically set. If "ModelSim Verilog" is chosen, this option is not set.

These options are then passed on to NGD2VHDL, NGD2EDIF, or NGD2VER.
AR# 13288
Date 08/11/2003
Status Archive
Type General Article