UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 13292

4.1i XST - XST generates incorrect logic because of a function that converts a string-to-std_logic_vector

Description

Keywords: VHDL, function, string, std_logic_vector

Urgency: Standard

General Description:
If I perform a string conversion-to-std_logic_vector function in VHDL, incorrect logic is generated.

Solution

This problem is fixed in the latest 4.1i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 4.1i Service Pack 3.
AR# 13292
Date Created 11/30/2001
Last Updated 08/06/2003
Status Archive
Type General Article