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AR# 13362

ISE4.1SP2 XST - "ERROR:XST:900 - "file_name.v", line XX: Reset or set value must be constant in <port_name[x]>."

Description

Keywords: 4.1, ISE, WebPACK, Verilog, XST, error

Urgency: Standard.

General Description:
When I compile Verilog code into XST, the following error message is reported:

"ERROR:Xst:900 - "file_name.v", line 100: Reset or set value must be constant in <port_name[XX]>."

Solution

This error occurs when a clock enable is used to enable the signal in the error message. The clock enable is also listed as an asynchronous signal in the sensitivity list.

For example:

always @(posedge clkx or posedge clkx_enable or posedge rst)
begin

if (rst) begin
...
end

else if (clkx_enable) begin

if (condition) error_signal <= value;

end

end


To work around this problem, remove the clock enable signal from the sensitivity list.
AR# 13362
Date Created 12/10/2001
Last Updated 08/06/2003
Status Archive
Type General Article