General Description: My HDL instantiates registers multiple times in the top level. How can I ensure those registers are not optimized together so that they can be pushed into the output IOBs with MAP -pr o?
To make sure Synplify does not try to place the registers into the input IOBs, set syn_useioff = 0. This will ensure that the IOB=TRUE constraint will not be in the EDIF output and will give MAP control over pushing the registers.
To make sure Synplify preserves registers so they can be pushed out to the IOBs, set syn_preserve = 1 on the register. Otherwise, Synplify will merge like registers, preventing them from being pushed into the IOBs.