We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 13451

4.2i PAR - Gigabit I/O pin placement can affect minimum clock period


Keywords: INFINIBAND, XAUI, GT, channel bond, Virtex-IIPro, Virtex-II Pro

In timing-critical standards INFINIBAND and XAUI, the placement of the GT Channel Bonding connects is critical. If the CHBONDO-to-CHBONDI connection is not properly made, timing will not be met for these standards.


If the GT pins are placed on the same edge of the device, PAR can optimize the CHBONDO-to-CHBONDI connection for speed.

NOTE: This Answer Record applies to timing-driven routing only.
AR# 13451
Date 10/20/2008
Status Archive
Type General Article
Page Bookmarked