General Description: In Simulink, I have used the FIR block and have generated a multi-channel FIR in my design. When I run VHDL simulation, simulation mismatch errors are reported.
This problem is in the VHDL wrapper that is written out by the System Generator. This is NOT a bug in the FIR filter (EDIF netlist) that is created from CORE Generator. If anything other than a Gateway-In or a multi-rate block (such as an up or down sampler) is connected to the inputs of the multi-channel FIR block, these errors will occur.
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