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AR# 13553

LogiCORE PCI-X - Why do the M_DATL_VLD and M_DATH_VLD signals assert with a split transaction?


General Description:

The PCI-X Design Guide states that the M_DATL_VLD and M_DATH_VLD signals are asserted when a valid data transfer occurs on the PCI bus. However, these signals also assert when the target terminates with a split completion. Why does this happen?


M_DATL_VLD and M_DATH_VLD will assert when the target terminates with a split completion even though a valid data transfer did not occur on the bus. To verify that a split completion occurs, your application must also monitor M_SPLIT.

By default, M_SPLIT will assert once cycle after M_DATL_VLD and M_DATH_VLD.

This may not work in some designs, because by the time M_SPLIT asserts, it may be to late to discard the data. In this case, you may advance the assertion of M_SPLIT by setting Bit 509 of the CFG bus in the cfg.v or cfg.vhd file to a Logic 1. This will cause M_DATL_VLD, M_DATH_VLD, and M_SPLIT to assert on the same clock cycle.

The following information will be added to page 3-11 in the next version of the PCI-X Design Guide:

"To advance the target split response status indicator by one clock cycle, set the following bit:

assign CFG[509] = 1'b0;"

AR# 13553
Date 12/15/2012
Status Active
Type General Article