AR# 13598


7.1i Timing - A PCF contains both BELs for a DDR when it should contain only one


General Description:

I would like to constrain each flip-flop of a DDR separately, so I place them into separate groups using the following constraints:


INST "ddr1d/FDDRCPE1/FF0" TNM = "reg1";

INST "ddr1d/FDDRCPE1/FF1" TNM = "reg2";

However, when I look at these constraints in the PCF, the same BELs are both contained there:


TIMEGRP "reg1" = BEL "ddr1d/FDDRCPE1/FF1" BEL "ddr1d/FDDRCPE1/FF0" ;

TIMEGRP "reg2" = BEL "ddr1d/FDDRCPE1/FF1" BEL "ddr1d/FDDRCPE1/FF0" ;

As a result, the following constraints cover the same paths in TRCE, so I cannot specify different OFFSETs for two registers (clocks) in the DDR:

OFFSET = OUT 10 nS AFTER COMP "clk" TIMEGRP "reg1" ;

OFFSET = OUT 15 nS AFTER COMP "clk" TIMEGRP "reg2" ;

What is the correct way to separately group the BELs of the DDR register?


You can use a TNM_NET on the data-in or clock nets. When a TNM_NET is traced into one of these pins, only the corresponding BEL will be grouped. Of course, if the clocks are merely inverted versions of each other, using the clock net might be difficult (and the data-in net might not be easily accessible in a synthesized design).

In this case, another option is to put the entire DDR into a group, then extract subgroups with the RISING and FALLING qualifiers. (Please see the Constraints Guide in the Software Manuals for more details on RISING and FALLING keywords.)

The second option is to use the obscure UCF pin syntax to apply the TNM directly to the clock pin.

For example:

PIN "ddr1d/FDDRCPE1.C0" TNM = reg1;

PIN "ddr1d/FDDRCPE1.C1" TNM = reg2;

This works the same as a TNM_NET on the clock net, except that it can be isolated to a specific clock pin.

Using TNM_NET for grouping on DCM output clocks allows the tools to differentiate between the two BELs, enabling you to apply different offsets to two different BEL flops in a DDR IOB.

AR# 13598
Date 01/18/2010
Status Archive
Type General Article
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