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AR# 13605

CPLD - Pin locking causes design to not fit into the device

Description

A design does not fit with pin/node locks assigned, but does fit when no design constraints are given (when "Use Design Constraints" is disabled in the ISE GUI).

Solution

(This resolution is only applicable for designs that meet the above description.)

Bring up the fitter report (.rpt) of the design that did not fit. A section in the first few pages of the fitter report reads FB Summary. This should contain some function blocks that have resource usage relatively close to the maximum.

For example:

For an XC9500 -- a function block with 33+ function block inputs

For XC9500XL or XV -- a function block with 49+ function block inputs

For CoolRunner XPLA3 or CoolRunner-II -- a function block with 38+ function block inputs.

The purpose of the following suggestions is to relieve the congestion in that function block:

1. Release the pin locks on the outputs in that function block. This allows the fitter to place those output signals in a less congested function block.

2. Try to buffer the logic in that congested function block.

For Example:

15 Product term (PTerm) equation -> output buffer

buffered:

10 PTerm equation -> 6 PTerm equation* -> output buffer

* 6 instead of 5 because 1 Pterm is the output of the previous level, the 10 PTerm equation.

This breaks up the logic. The first level of logic is free to be placed in any function block, and the second level of logic will be placed in the same function block as the output pin for that signal. So instead of a function block requiring 15 distinct p-terms, it now needs only 5, and a different function block needs 10 p-terms.

All synthesis tools will attempt to perform optimization and collapse your buffer node into one level of logic. The methods that prevent this from happening vary from vendor to vendor. Please check with your individual vendor for details on how to do so.

In XST, this is done using the following syntax:

VHDL:

attribute KEEP : string ;

attribute KEEP of netname : signal is "TRUE";

Verilog:

//synthesis attribute KEEP of netname

If you are using a different synthesis tool, and see that the node is indeed surviving synthesis but is still being removed by the fitter, try attaching a KEEP constraint within the UCF.

net netname KEEP;

Re-fit the design, making sure that you enable Use Design Constraints.

AR# 13605
Date Created 08/29/2007
Last Updated 12/15/2012
Status Active
Type General Article