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AR# 13611

CPLD - My device fails the verify operation


My attempts to verify the JEDEC in a Xilinx CPLD result in errors.


If a device fails to verify, it was probably either programmed with a different JEDEC, or was misprogrammed. Re-program the device, and re-verify. If the device still fails to verify (or program), there might be a problem with your programmer or your JTAG connections.

If the device is a CoolRunner XPLA3, please verify that you have not disabled the JTAG pins. For more information on this, please see (Xilinx Answer 8455).

Programmer tips:

1. Ensure that you are using the latest version of the programmer software.

- If you are using the iMPACT programmer, service packs can be downloaded from:

- If you are using the Xilinx HW-130 programmer, the latest version can be found at:


2. Contact the programmer manufacturer to see if there are any known issues.

JTAG tips:

1. If you are having problems communicating with the device via JTAG at all, you might have signal integrity issues, or your JTAG port connections might be incorrect.

2. If you are having intermittent problems programming and verifying, this is likely a noise issue. This can be identified by using the "IDCODE Looping" feature within iMPACT (formerly JTAG Programmer).

3. If you have no problems detecting the device via JTAG, but cannot verify, the device might have the readback security feature enabled. In this situation, there is no way to verify the JEDEC against the pattern programmed into the CPLD. At this point, we would recommend erasing the device and re-programming it without the read security bit set.

4. For more assistance, please see the JTAG Problem Solver at:


AR# 13611
Date 12/15/2012
Status Active
Type General Article
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