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AR# 13630

CPLD - A design functions properly in one recommended operating temperature range, but not in another


General Description:

A Xilinx CPLD functions properly in one temperature range, but not in another. In both cases, the device is within the recommended operating temperature as stated in the device data sheet, and it passes timing simulation.


Design fails at higher temperatures

If the design fails at high temperatures, it is likely that the design is running too fast for the device. As with all CMOS-based devices, the colder the device, the faster logic propagates. Consider using a using all macrocells in high speed mode as opposed to low power mode (XC9500/XL/XV families only), implementing the design using Speed optimization (instead of Balanced or Density), and adding timing constraints to the failing path.

Design fails at colder temperatures

If the design fails at cold temperatures, the problem is probably an asynchronous path. This is often a "race" condition between two logic paths where one path may be faster than the other, but not across the temperature range. This may be corrected by adding a register to capture the data after sufficient time for the "race" to be evaluated. It can also be fixed by placing one of the paths in low power mode, which will slow down the propagation delay. Registering the data is the proper method of fixing this problem.

AR# 13630
Date 02/19/2013
Status Active
Type General Article