# AR# 13645

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## Description

How do I calculate the CLK0 and CLK2X output jitter of the DLL or DCM given a specific input jitter? How do I use this to constrain my design?

NOTES:

1. For the best estimate, the input jitter must be measured at the clock input pin of the FPGA.
2. This Answer Record applies to all devices that contain CLKDLL or DCM components.

## Solution

Definitions

JIN = The input period jitter as measured at the clock input pin of the FPGA
JSpec = DLL output period jitter as specified in the data sheet
JTotal = The total expected output period jitter

All calculations must be performed using the peak-to-peak measurement/specification. The period jitter specifications are available as follows:

- For Virtex-II, Spartan-3, and later devices, refer to the appropriate data sheet at:

http://www.xilinx.com/support/documentation/index.htm
- For Virtex-E/Spartan-IIE devices, use the specifications as described in (Xilinx Answer 13771).

- For Virtex/Spartan-II devices, the characterization data for period jitter is not available. Use the Virtex-E/Spartan-IIE data (Xilinx Answer 13771) for your calculation.

- CLKFX:

- For Spartan-3, Virtex-II, Virtex-II Pro, Virtex-4, and Virtex-5 you can obtain CLKFX jitter specifications from the Architecture Wizard tool. See (Xilinx Answer 12667) for more information.

- To calculate the CLKFX output jitter of Spartan-3A/-3AN /-3A DSP, you can use the Spartan-3A Jitter Calculator at:

http://www.xilinx.com/support/documentation/data_sheets/s3a_jitter_calc.zip.

Calculation

The JTotal is calculated as the RMS (root mean square) of JIN and J:

JTotal = (JIN^2 + JSpec^2) ^1/2

Example calculation for a Virtex-II device with a CLK0 DCM output:

Given JIN = 100 ps peak-to-peak
JSpec = +/- 100 ps = 200 ps peak-to-peak
JTotal = (100^2 + 200^2)^1/2 = 224 ps

Consequently, the total jitter in the FPGA is 224 ps peak-to-peak or +/- 112 ps. To account for jitter in your design, subtract 112 ps from your period constraint.

For example, if you expect to run your design at 100 MHz (10 ns period), constrain the design to 9.888 ns.

For information on how jitter can affect your design, refer to the following white paper:

"Jitter - Variations in the Significant Instants of a Clock or Data Signal "

http://www.xilinx.com/support/documentation/white_papers/wp319.pdf
AR# 13645
Date 12/15/2012
Status Active
Type General Article
Devices
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