I have made changes and saved them in FPGA Editor. When I run a re-test in Timing Analyzer, the process crashes and reports the following error message:
"FATAL ERROR: timing baswoffsetpref.c:582:1.51 - Clock arrival not found! Process will terminate."
(This error only occurs when I attempt to analyze against auto-generated constraints.)
This problem occurs because, when the changes are made and saved in FPGA Editor, the PCF file interprets the components as the NCD. When this conflict is found, the above error is reported.
To avoid this problem, make the required change in the UCF and re-run the MAP and PAR processes with all the changes made. You may then run Timing Analyzer with no further problems.