AR# 13681


7.1i Timing Analyzer/TRCE (Trace) - "WARNING:Timing:2589 - Fixed phase shift in use on DCM 'xxx' without proper period..."


General Description:

The following incomplete warning message is reported:

"WARNING:Timing:2589 - Fixed phase shift in use on DCM dcm_rx2 without proper period or frequency specification. A period or frequency constraint must be applied to the DCM input net in order for a phase shift to be calculated."

What does this warning mean? How do I fix it?


The fixed phase shift feature of the DCM is specified as a fraction of the period. In hardware, the actual delay is determined by the clock period recovered from the DLL.

However, static timing analysis does not know the frequency of the clock signal that will be applied at its input pin. Without this information, the timing tools cannot determine how large a phase shift will be seen in the hardware and will thus ignore the fixed phase shift of the DCM.

You can resolve this by passing the clock period information to the timing analysis tools via the placement of a PERIOD constraint on the input clock. This is usually performed in the user constraints file (".ucf") by the user or the Xilinx Constraints Editor.

For example:

A net "clkin" would have the following two lines in the ".ucf" file:

NET "clkin" TNM_NET = "clkin_grp";

TIMESPEC "TS_clkin" = PERIOD "clkin_grp" 15 ns HIGH 50 %;

With this clock period of 15 ns, the timing tools can adjust for DCM phase shift correctly.

More information on PERIOD and timing constraints is available in the "Timing and Constraints" Tech Tip:

AR# 13681
Date 01/18/2010
Status Archive
Type General Article
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