General Description: When synthesizing a 4.1i design, XST may return a "parse error" if it detects that the Verilog design is syntactically wrong.
This problem has been fixed with the release of software version 5.1i.
This error may occur when a Verilog file does not have an "endmodule" to close the file. The tools parse through the source code, then move on to the unisim_comp.v file; however, as they do not see an "endmodule" keyword before they get to the unisim_comp.v file's "module" keyword, the tools will flag a syntax problem.
To resolve this error, look through the Verilog source files and add the keyword "endmodule" to any Verilog files that have an open "module" declaration.
When specifying constants, the Verilog specification allows you to omit the width of the constant, which allows the synthesis tool use a default constant width of 32 bits.
To work around this, specify the width of the declared constant.