AR# 1374: Foundation XVHDL: How to use Bidirectional I/O
AR# 1374
Foundation XVHDL: How to use Bidirectional I/O
Description
Keywords: bidi, metamor, pin, inout
Versions: F6.x, F1.3/F1.4
Urgency: Standard
General Description:
Bidirectional I/O signals can be described behaviorally in the VHDL code by using an 'inout' port in the entity and with the output described as tri-statable in the architecture. XVHDL will infer the appropriate types of I/O components.
Please note that with the XVHDL compiler, you must describe the entire bidirectional pin, including output tristate, in the top-level VHDL file. For more information on this topic, please see (Xilinx Solution 2591).
Solution
--Example of behavioral description of bidirectional I/O --Note that in this example the output is both tri-stated --and registered. An output flip-flop with tri-state enable --(OFDT) will be inferred.
library IEEE; use IEEE.std_logic_1164.all;
entity BIDIR is port (DATA: inout std_logic; NOT_DATA: out std_logic; CLK, A, B: in std_logic; ENABLE: in std_logic); end BIDIR;
architecture INVERT of BIDIR is signal IN1: std_logic; signal OUT1: std_logic; begin IN1 <= A and B;
process (CLK) begin if CLK'event and CLK='1' then --CLK rising edge OUT1 <= IN1; end if; end process;
--Tri-state buffer DATA <= (OUT1) when ENABLE='1' else 'Z'; NOT_DATA <= not DATA;
end INVERT;
-- This example describes 4-bit wide tri-stated I/O bus.
library IEEE; use IEEE.std_logic_1164.all;
entity BIDIR2 is port (DATA: inout std_logic_vector (3 downto 0); NOT_DATA: out std_logic_vector (3 downto 0); A, B : in std_logic_vector (3 downto 0); CLK : in std_logic; ENABLE: in std_logic); end BIDIR2;
architecture bidi_bus of BIDIR2 is signal IN1: std_logic_vector (3 downto 0); signal OUT1: std_logic_vector (3 downto 0); begin IN1 <= A and B;
process (CLK) begin if CLK'event and CLK='1' then --CLK rising edge OUT1 <= IN1; end if; end process;
--Tri-state buffer DATA <= (OUT1) when ENABLE='1' else "ZZZZ"; NOT_DATA <= not DATA;