UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx - Adaptable. Intelligent.
  2. Support
  3. AR# 1375: Foundation XVHDL: Using Global Buffers

AR# 1375

Foundation XVHDL: Using Global Buffers

Description


Versions: F6.x, F1.3/F1.4



Urgency: Standard



General Description:



Xilinx FPGAs feature global buffers which provide low skew

and high drive for clocks and other control signals with high

fan-out. Consult the Xilinx Libraries Guide for more

information on the various types of global buffers available

with the various FPGA families.



There are 3 ways to use global buffers with Foundation XVHDL:

1. Automatic Insertion

2. Xilinx_BUFG Attribute

3. Instantiation



See also (Xilinx Solution 1473) for information on

controlling the number of inferred global buffers.



**Note that this solution applies to the Metamor XVHDL compiler

only. If using the Express HDL compiler, you may control the

insertion of Global Buffers using the Express Constraints GUI.

Solution


Automatic Insertion

-------------------

XVHDL automatically attaches a BUFG to any input port signal

which directly drives a clock pin. Depending on which Xilinx

device family is selected in the Foundation Project Manager,

a limit is set as to the maximum number of BUFGs which can be

automatically inserted into the synthesized XNF file, based

on the architectural capabilities of the device.



When XVHDL inserts a BUFG on a clock net as described above,

the BUFG takes the place of an IBUF. Therefore, a dedicated

global buffer input pad on the device is used.



Xilinx_BUFG Attribute

---------------------

It is also possible for XVHDL to insert a BUFG on any

specified input port signal, regardless of whether it is a

clock signal or not. Use the 'Xilinx_BUFG' attribute as

shown below to access this feature. Again, this BUFG

replaces the IBUF, and thus uses a dedicated global buffer

pad. This attribute will not attach a BUFG to an internal

signal. Only apply this attribute to top-level port signals.



attribute Xilinx_BUFG: boolean;

attribute Xilinx_BUFG of <port_name>: signal is true;



--Example of using the Xilinx_BUFG attribute



library IEEE;

use IEEE.std_logic_1164.all;



entity USE_BUFG is

port (CLK, IN1, CE: in std_logic;

OUT1: out std_logic);



attribute xilinx_bufg: boolean; --declare the attribute

attribute xilinx_bufg of CE: signal is true;

--CE will use a BUFG

end USE_BUFG;



architecture TEST of USE_BUFG is

begin

process (CLK)

begin

if (CLK'event and CLK='1') then

if CE='1' then

OUT1 <= IN1;

end if;

end if;

end process;

end TEST;



Instantiation

-------------

Global buffers may also be instantiated. Use this method to

drive a global buffer with an internally generated signal, or

to control the specific type of global buffer used. If, for

instance, in an XC4000 design, you wish to specify the use of

a BUFGP rather than the generic BUFG, you may instantiate the

BUFGP, as shown in the example below.



If you wish to use the dedicated input pad for the

instantiated global buffer, you must use the 'inhibit_buf'

attribute on the input signal port to prevent XVHDL from

inserting an IBUF at the input. This IBUF would prevent the

global buffer from using the dedicated input pad. If you

wish to use an input pad other than the dedicated global

buffer input pad, do not use the 'inhibit_buf' attribute.

XVHDL will treat the signal like an ordinary input and insert

an IBUF between the pad and the global buffer.



--Example of instantiating a global buffer



library IEEE;

use IEEE.std_logic_1164.all;



entity USE_BUFG is

port (CLK, IN1: in std_logic;

OUT1: out std_logic);



attribute inhibit_buf: boolean; --declare the attribute

attribute inhibit_buf of CLK: signal is true;

--This attribute prevents XVHDL from inferring an IBUF

--on the CLK port, which allows the Xilinx software to

--use the dedicated clock input pin.

end USE_BUFG;



architecture TEST of USE_BUFG is

signal BUFGP_OUT: std_logic;

component BUFGP

port (I: in std_logic;

O: out std_logic);

end component;

begin



U1: BUFGP port map (I => CLK, O => BUFGP_OUT);



process (BUFGP_OUT)

begin

if (BUFGP_OUT'event and BUFGP_OUT='1') then

OUT1 <= IN1;

end if;

end process;



end TEST;
AR# 1375
Date 12/16/2011
Status Archive
Type General Article
Page Bookmarked