We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 13769

4.1i Timing Analyzer/TRCE (Trace) - DCM fixed phase shift is not taken into account for variable shift mode


Keywords: timing, TRCE, DCM, phase, shift, variable, fixed, clock

Urgency: Standard

Problem Description:
When I perform static timing analysis on a design with a DCM in variable phase shift mode, the fixed phase shift is not accounted for. Why?


We are currently investigating the inclusion of the fixed phase shift in the timing analysis when the DCM is in variable mode.

To represent phase in the design, a PERIOD constraint may be applied to the output of the DCM with the fixed phase modeled using the PHASE keyword.

For example:

TIMESPEC "TS_clk33_3p75" = PERIOD "clk33_3p75_grp" "TS_clk133" * 4.0 PHASE + 3.75 ns;

NOTE: This only applies when the DCM is in VARIABLE mode, not when it is in FIXED phase shift mode.

AR# 13769
Date 10/07/2003
Status Archive
Type General Article