We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 1380

Configuration takes a long time


FPGAs will go into their start up sequences when two
criteria are met.
1. The length count and the FPGAs internal counter
(which keeps track of the number of CCLKs the FPGA
has received since init went high) are exactly equal.
2. The device's full flag is set at the time the
first condition occurs, meaning that the device has
received all of its configuration data.

When a configuration process takes an excessively long
time--say 10's of seconds-- but does eventually configure,
this often means that the length count that has been read
into the FPGA has somehow been corrupted. Causing the length
count and the internal counter to be equal before the devices
full flag is set. This means that the device must be clocked
2^24 more times before the length count and internal counter
will be equal again.

In master serial mode, this can happen in a couple of ways:

1. The LCA receives bad data at the beginning of the
configuration process, before the PROM has finished clearing
itself and starts outputing data to the LCA.

2. Noise on the board corrupts the length count.

To verify that this is the problem, you can read the first
40 bits of data coming out of the dout pin of the FPGA and
compare them with the first 40 bits of the bitstream.



To prevent the LCA from reading data from the PROM before the PROM has actually started to send data to it, program the PROM for active low RESET, and tie RESET/OE of the PROM to the INIT pin of the LCA.


Reduce noise on the board. Some things you can do:

- add decoupling capacitors to GND and VCC
- avoid routing fast-switching outputs to adjacent pins on the
AR# 1380
Date 09/30/2005
Status Archive
Type ??????
Page Bookmarked