We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 13829

5.1i Timing Analyzer - "Warning: NCD:391 - The component 'xxx' is being ignored, as it has been edited..."


General Description:

The following warning is reported:

"Warning: NCD:391 - The component "xxx" is being ignored, as it has been edited in such a way as it is no longer applicable."

What does this warning mean? How do I resolve it?


This error indicates that a super BEL has been created. A super BEL is a collection of basic elements (BELs) that can no longer be analyzed separately by the timing tools (TRCE, Timing Analyzer, PAR, FPGA Editor).

A super BEL is created by either using a hard macro (.nmc file), or by modifying the configuration of a logic element in the .ncd file, using FPGA Editor. For example, modifying a slice element to include the LUT can create a super BEL from the slice. The timing tools will no longer list the BEL names of the LUT and the flip-flop, and will only list the slice name. Super BELs are not always analyzed correctly.

To resolve this, implement the change performed in FPGA Editor into the design flow. For the above LUT/flip-flop example, instantiating the LUT in front of the flip-flop into the HDL code will prevent a super BEL from being created.

AR# 13829
Date 01/18/2010
Status Archive
Type General Article