In designs that I created before using 4.1i Service Pack 3, fewer paths were analyzed. What changed in 4.1i Service Pack 3 that created these extra paths? Can I turn them off?
The timing parameter "tshckof5" was enabled in 4.1i Service Pack 3. This parameter is a synchronous point that begins at a distributed RAM slice. It represents the data presented to the output of a distributed RAM after a synchronous write. Previously, only asynchronous paths through the distributed RAM were analyzed.
To disable these paths, simply use normal TIG constraint methods.
Alternatively, the "tshckof5" delay parameter can be turned off with the following UCF constraint:
NOTE: This will turn off all paths that contain this delay parameter.