General Description: FPGA Express will occasionally create netlists net names that differ only by case (e.g., "n48" and "N48")
The EDIF netlist format is case-sensitive, so this is legal EDIF. However, many EDIF simulators (including the Foundation simulator) are not case- sensitive. The Foundation simulator will issue a warning in the console and in the aldec.log file. The second net of the pair is ignored, leaving it undefined in simulation.
It can be very difficult to find the warning message mentioned above. Many users elect not to look at the simulation netlist log when only warnings are issued, as most of the warnings can safely be ignored. When a simulation signal becomes unknown for no apparent reason, this is often the first sign of this problem.
The only way to work around this situation is to manually edit the netlist file so that the duplicate nets are eliminated.