In the best case scenario, the LogiCORE should assert TRDY# one cycle after it asserts DEVSEL#. Currently, however, LogiCORE asserts TRDY# on the same cycle as DEVSEL#. Why is this occurring, and what can I do to fix it?
If the application is ready to transfer data as a target by asserting S_READY when the transaction begins, the earliest that LogiCORE will assert TRDY# is one cycle after it asserts DEVSEL#.
If TRDY# is asserting at the same time as DEVSEL#, it is possible that two devices on the bus are claiming the same transaction.
For example, if the base address space of another agent on the bus is overlapping with the base address space of the Xilinx core, and the other agent has a faster decoding speed than the Xilinx core, the other agent may assert TRDY# at the same time the Xilinx core asserts DEVSEL#.
Check the base address ranges of the other devices on the bus to see if overlapping with the Xilinx core is occurring. If this is happening, some type of configuration error exists, as the address space of two different BARs should not overlap .