General Description: I place location constraints (LOCs) on bussed I/O pads from the Xilinx libraries (IPAD4/8/16, OPAD4/8/16, and IOPAD4/8/16), but the LOCs are ignored.
One way to work around this problem is to copy the Xilinx library component to a user library; this allows you to edit the schematic underneath, adding the LOC attributes.
You may need to make multiple copies of the component. For example, if you wish to place two IPAD4 components, each one with a different set of LOC attributes, you must make two copies of the IPAD4 and place different LOCs inside each one. (Please see (Xilinx Answer 1657) for instructions on copying a Xilinx library component.)
After you copy a component, edit the schematic under the symbol to add the LOC attributes:
1. Open Schematic Editor. 2. Select File -> Open and select the copied macro from the list of macros. 3. Add the LOC attribute to the individual pad symbols.
You may also use the LogiBLOX utility to work around this problem. (NOTE: LogiBLOX is only available with FPGA designs.)
1. In Foundation Project Manager, select Tools -> LogiBLOX. 2. Select Module Type -> Pads (either input, output, or bidirectional). 3. The Pad LOC attribute specifies the pin location for an I/O pad.
To assign a location to a specific bit, precede the location with a bit identifier. You may assign multiple bits by using a period as a separator. For example, with a bus width of 8 bits, you could have the following assignment:
This specification assigns Bit 0 to Pad 44, Bit 2 to Pad 45, and Bit 7 to Pad 46.
NOTE: Commas will not work as separators between bit assignments.
Using a UCF (User Constraints File).
For example, a bus named "A[7:0]" (between the IPAD8/OPAD8 and IBUF8/OBUF8) may be pin-locked by using the following syntax in the UCF:
NET A<7> LOC = P18; NET A<6> LOC = P19; NET A<5> LOC = P20; NET A<4> LOC = P23; NET A<3> LOC = P24; NET A<2> LOC = P25; NET A<1> LOC = P26; NET A<0> LOC = P27;
If the PAD is in a lower level of hierarchy (i.e., anything but the top level), use the following syntax:
NET INSTANCE_NAME/A0 LOC = P15;
where INSTANCE_NAME is the name of the hierarchical block, and A0 is the 0 bit of the A bus. Note that you should NOT use the angle brackets <> around the bit number of the bus.
If you are designing for a CPLD, you may also use the GYD file to lock your pins.
The GYD file is created automatically when the design is fit, and it contains the pin-out of the fitted design. To modify or change the pin assignments, edit the .gyd file with a text editor.
After you modify the GYD file, when you implement the design, be sure that the appropriate GYD file is selected in the "Implementation Options" dialog box. This will ensure that the pin-out in the GYD file is used.