UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 13975

XST - "ERROR:HDLParsers:3340 - Project file .prj names two source files, .vhd and .vhd, that both define the same primary unit, "

Description

General Description:

When I compile a VHDL design, XST reports the following error:

"ERROR:HDLParsers:3340 - Project file <project>.prj names two source files, <file1>.vhd and <file2>.vhd, that both define the same primary unit, <my_entity>"

Solution

This error indicates that multiple instances of the named entity were found during HDL parsing. Port names are irrelevant; the name must be unique for each entity within your project.

To resolve this conflict, remove one of the instances from the project, or modify the name of one of the entities.

AR# 13975
Date Created 08/29/2007
Last Updated 12/15/2012
Status Active
Type General Article