When I compile a VHDL design, XST reports the following error:
"ERROR:HDLParsers:3340 - Project file <project>.prj names two source files, <file1>.vhd and <file2>.vhd, that both define the same primary unit, <my_entity>"
This error indicates that multiple instances of the named entity were found during HDL parsing. Port names are irrelevant; the name must be unique for each entity within your project.
To resolve this conflict, remove one of the instances from the project, or modify the name of one of the entities.