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AR# 14032

XST - "ERROR:HDLParsers:3312 - .vhd Line xx. Undefined symbol 'std_logic_vector'. / ERROR:HDLParsers:3313 - .vhd Line xx. Undefined symbol 'xxx'. Could it be 'yyy'?"


General Description:

When I synthesize a VHDL design with XST, the VHDL parser reports one of the following errors:

"ERROR:HDLParsers:3312 - <file>.vhd Line xx. Undefined symbol 'std_logic_vector'."

"ERROR:HDLParsers:3313 - <file>.vhd Line xx. Undefined symbol 'xxx'. Could it be 'yyy'?"

Other XST VHDL errors might follow.


This error occurs if the symbol or type that is being accessed is not declared in the VHDL source file, and if the 1164 package of the IEEE libraries is not listed as follows:

USE ieee.std_logic_1164.ALL;

This message also occurs for user symbols, types, or component instantiations if they are not declared. If the instance is similar in name to one that has been declared, XST will suggest that instance when reporting Error 3313.

If the unknown component is a Xilinx primitive, refer to the UniSim primitive library to avoid having to declare the component. At the beginning of your VHDL file, use the following library declaration and usage statements:

library unisim;

use unisim.vcomponents.all;

You will receive the HDLParsers:3313 error if you have an alias declared in a package and you use the alias inside your entity/architecture.

This problem is fixed in the latest 5.2i Service Pack, available at:

The first service pack containing the fix is 5.2i Service Pack 1.

AR# 14032
Date 12/15/2012
Status Active
Type General Article