Can the unused JTAG pins of a Xilinx CPLD device be left unconnected?
The devices addressed by this Answer Record are:
XC9500, XC9500XL, XC9500XV, and CoolRunner XPLA3 have internal pull-ups on TDI and TMS.
CoolRunner-II devices have internal pull-ups on TDI, TMS, and TCK.
Xilinx recommends using external pull-up resistors on the JTAG input pins, TDI, TMS, and TCK. The value of these resistors can be customized per your application and JTAG chain length; for a single device the value of 4.7k Ohm is suggested.
Internal pull-up resistors are present on these JTAG input pins. However, external termination will allow for increased tolerance of noisy environments.
For XPLA3 devices, tie the Port-Enable pin to ground if the JTAG pins are dedicated for JTAG use. For more information on Port-Enable, see (Xilinx Answer 8455).
For other common CPLD questions, see the CPLD FAQ (Xilinx Answer 24167).