.v Line xx. Illegal left hand side of procedural continuous assignment."">
When a Verilog source file is compiled, XST issues the following error:
"ERROR:HDLCompilers:42 - <file>.v Line xx. Illegal LHS of procedural continuous assignment."
This error occurs when a signal has been declared as a register data type instead of a net data type.
When you perform a continuous assignment in a concurrent statement, use a net data type (typically "wire") to allow data to be instantly updated.