General Description: When compiling a Verilog source file, XST issues the following error:
"ERROR:Xst:1022 - <file>.v Line xx. Illegal output port specification for port: '<my_port>'."
This error most commonly occurs when the output of a submodule is connected to a signal on the upper level that is defined as a register data type. Because the value is not being assigned in a procedural assignment, it should be declared as a net data type (wire).
Here is a simple example:
<code> module top (a, b); input a; output b; wire b; // this must be wire, not reg