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AR# 14083

4.1i XST - "ERROR:Xst:1022 - <file>.v Line xx. Illegal output port specification for port: '<my_port>'"

Description

Keywords: XST, Verilog, 1022, output, port, submodule

Urgency: Standard

General Description:
When compiling a Verilog source file, XST issues the following error:

"ERROR:Xst:1022 - <file>.v Line xx. Illegal output port specification for port: '<my_port>'."

Solution

This error most commonly occurs when the output of a submodule is connected to a signal on the upper level that is defined as a register data type. Because the value is not being assigned in a procedural assignment, it should be declared as a net data type (wire).

Here is a simple example:

<code>
module top (a, b);
input a;
output b;
wire b; // this must be wire, not reg

lower U1 (.in(a), .out(b));

endmodule

// lower is declared elsewhere
</code>
AR# 14083
Date Created 03/06/2002
Last Updated 08/06/2003
Status Archive
Type General Article