I have successfully generated my DDS v4.1, but when I run the design through the Xilinx 4.2i or 5.1i implementation tools, errors similar to the following are reported:
"ERROR:Place:1751 - Structured logic associated with an F7 configuration could not be placed. This logic requires a very specific relative placement. The relative placement required by the logic was impossible to resolve. The structured logic could not be placed in the relative placement form required. This is due to the fact that the component N4568 is already contained in an rpm that will not allow the logic to be placed in the legal form."
When I run BitGen after PAR from the command line, the following errors are reported:
"ERROR:DesignRules:14 - Blockcheck: The component "N1306" has not been placed."
"ERROR:DesignRules:14 - Blockcheck: The component "N1352" has not been placed."
This issue is currently under investigation.
To work around this problem, turn off Placement in the CORE Generator GUI when creating the DDS core; you can accomplish this by deselecting "Layout: Create RPM".