AR# 14161: 8.1i ISE - How do I prevent the red question marks that appear for instantiated primitives in the hierarchy of the "Sources in Project" window?
8.1i ISE - How do I prevent the red question marks that appear for instantiated primitives in the hierarchy of the "Sources in Project" window?
Keywords: VHDL, define, definition
The "Sources in Project" window in Project Navigator displays files with red question marks when I instantiate components that are Xilinx primitives. The red question marks indicate that Project Navigator does not know the definition of the underlying module. Is there a way to prevent the red question marks from appearing for Xilinx primitives?
Even though a primitive causes a red question mark to appear in the hierarchy, the primitive will be correctly added to the design if it was instantiated correctly. To avoid the question marks, add the following to your VHDL source file and whatever synthesis directives are necessary to prevent the synthesis tool from trying to synthesize the simulation library:
-- synthesis translate_off library unisim; use unisim.vcomponents.all; -- synthesis translate_on