General Description: This Answer Record contains the known issues that are addressed in 4.2i IP Update#2 (also referred to as "E_IP2").
GENERAL KNOWN ISSUES
The E_IP2 IP update is only compatible with Xilinx CORE Generator 4.2i, which is included with the ISE 4.2i software. This IP update should not be used with any other versions of CORE Generator (such as version 4.1i and 3.1i or earlier).
1. DA FIR V7_0, DDC V1_0 GUI, and MAC FIR V1_0 In the GUI, an error that reports an invalid parameter in the COE file is displayed in a different base format. Please see (Xilinx Answer 14202).
2. MAC FIR V1_0 Incorrect results are given for 2-tap non-symmetric and 2- or 3-tap symmetric filters. Please see (Xilinx Answer 14242).
3. MAC FIR V1_0 After an initial load of the COE, the (COE) file can not be reloaded. Please see (Xilinx Answer 14323)
4. DDS V4_1 When the Xilinx Implementation tool is run with DDS v4.1, the following error is reported: "ERROR:Place:1751 - Structured logic associated with an F7 configuration could not be placed." Please see (Xilinx Answer 14122).
5. DDC V1_0, MAC V2_0, SID (Interleaver/Deinterleaver) V2_0 When a design is synthesized with the above cores, errors report that certain modules are not defined. Please see (Xilinx Answer 14341)
SIMULATION KNOWN ISSUES
1. When VHDL behavioral simulation models for Virtex-II Block Memories (blkmemv2dp_v2_0.vhd and blkmemv2sp_v2_0.vhd) are compiled, the VHDL "-93 Compliancy" switch must be used. Please see (Xilinx Answer 9734).
2. When XilinxCoreLib files are compiled using Synopsys VSS or VCSi, simulators report a number of warnings and errors. Please see (Xilinx Answer 12630).
3. When XilinxCoreLib files are compiled using Cadence NCVHDL, simulators report a number of warnings and errors. Please see (Xilinx Answer 14185).