.v Line xx. 'name' has not been declared"">


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AR# 14254

XST - "ERROR:HDLCompilers:28 - .v Line xx. 'name' has not been declared"


General Description:

When I compile a Verilog design with XST, the following error is reported:

"ERROR:Xst:926 - <file>.v Line xx. 'name' not declared."



Before using an instance of a signal, array, parameter, etc., the instance must first be declared. The XST parser scans a Verilog file from beginning to end, so any usage must be preceded by the declaration of that instance.

AR# 14254
Date 12/15/2012
Status Active
Type General Article
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