.v Line xx. 'name' has not been declared"">
When I compile a Verilog design with XST, the following error is reported:
"ERROR:Xst:926 - <file>.v Line xx. 'name' not declared."
Before using an instance of a signal, array, parameter, etc., the instance must first be declared. The XST parser scans a Verilog file from beginning to end, so any usage must be preceded by the declaration of that instance.