AR# 14259


4.2i XST - "FATAL_ERROR: Xst:Portability/export/Port_Main.h :116:"


Keywords: XST, Portability, FATAL_ERROR, VHDL, Verilog, export, Port_Main, ECS, schematics

Urgency: Standard

General Description:
When I synthesize a design using XST, the following error occurs:

"FATAL_ERROR:Xst:Portability/export/Port_Main.h:116: - This application has discovered an exceptional condition from which it cannot recover. Process will terminate. To resolve this error, please consult the Answers Database and other online resources at
EXEWRAP detected a return code of '1' from program 'C:/xilinx/bin/nt/xst.exe'

Done: failed with exit code: 0001"

(This may occur in either Verilog or VHDL flows.)



The use of certain unsupported templates has been known to cause fatal errors. Consult the XST User Guide to confirm whether the VHDL/Verilog syntax you are using is supported by XST.

Also, examine the XST log file to check for warnings prior to the fatal error. Resolve any conflicts and re-synthesize.


A number of issues can cause this error. Any fatal error occurs because XST has entered an unexpected situation. If an error of this type is reported, try the following:

1. Ensure that you are using the latest Service Pack. The XST development team fixes these types of errors quickly and releases the fixes in service packs, which are available at:

2. Isolate the cause of the fatal error. Typically, you may synthesize individual portions of the design to find the module/entity that contains the code causing the fatal error. Start with the most recent area in which you worked, and proceed backwards from there.

3. Send the design to Xilinx. The sooner the XST development team examines a test case or the actual design that leads to this error, the sooner the issue can be resolved. To send us your design, open a WebCase with Xilinx Customer Service at:


Certain switches will cause these fatal errors. (In the past, "Slice Packing" and "FSM Extraction" have been culprits.) Go to the "Synthesis Properties" dialog box to find and disable these options.


Illegal synchronous descriptions may also lead to fatal errors. For example, the following code will produce this fatal error:

if(CE='1') then
if(CLK'event and CLK='1') then
if (CLR'event and CLR='1') then -- This construct is not legal.
-- if (CLR='1') then -- Instead, use this construct.
qoutsig <="0000";
elsif(qoutsig="1001") then
qoutsig<=qoutsig + "0001";
end if;
end if;
end if;

The use of multiple event statements in one process "event" is illegal. Replace this line with a simple comparison that does not contain the 'event statement, and compilation will be successful.
AR# 14259
Date 08/06/2003
Status Archive
Type General Article
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