AR# 14264


Design Assistant for XST - Help Resolving "Xst:528 - Multi-source in Unit on Signal " Errors


Refer to this answer record for help resolving "Xst:528 - Multi-source in Unit <entity> on signal <sig>" Errors.

Note: This Answer Record is a part of the Xilinx Solution Center for XST (Xilinx Answer 38927). The Xilinx Solution Center for XST is available to address all questions related to XST. Whether you are starting a new design or troubleshooting a problem, use the Solution Center for XST to guide you to the right information.


1. This error appears when XST determines that there is contention on a particular signal. If the processes assigning values to this signal are mutually exclusive (as in the case of 3-state buffers), this message can be ignored.

However, in most cases, XST is able to determine when multiple drivers are illegal, and will stop synthesis soon after this message.

Check this signal and modify your code to avoid the existing contention.

2. In some cases, XST ties unconnected output ports to ground. If the output port is part of a 3-state bus, which in turn connects to another 3-state bus, then connecting one bit of the bus to ground will cause a multiple-driver error. Verify that this is not occurring in your design by searching for the following warning.

"WARNING:Xst:1305 - Output <dataout<23>> is never assigned. Tied to value 0."

To work around this issue, remove the unused output port.

3. This has also been seen in the following condition:

When there is an association signal named to_qvm_d4.Q_num.

When using association signal (to_qvm_d4.Q_num), XST will rename it to "to_qvm_d4_Q_num" during synthesis. There is signal named "to_qvm_d4_Q_num" in the same architecture. XST is confused with these two signals and errors.

To work around this issue, rename either of the two signals.

4. EDK Designs

For EDK Designs using bidirectional signals DIR=IO and THREE_STATE=FALSE, the external port name must match the connecting signal name exactly. NOTE: IOB_STATE is deprecated in future EDK versions.

For example, the MHS external port:

PORT DDR2_DQ_pin = DDR2_DQ, DIR = IO, VEC = [31:0]

should be changed to:

PORT DDR2_DQ = DDR2_DQ, DIR = IO, VEC = [31:0]

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
38927 Xilinx Solution Center for XST N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
40379 Design Assistant for XST Help understanding the XST report to resolve errors\warnings N/A N/A
AR# 14264
Date 12/15/2012
Status Active
Type General Article
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