When I synthesize a Verilog design in XST, the following warning appears:
"WARNING:Xst:863 - "<file>.v", line xx: Name conflict (<name> and <NAME>, renaming name as name_rnm0)."
Although Verilog is case-sensitive, any tools that run after synthesis may not be. To avoid potential contention at a later time, XST renames signals during analysis. The first instance name remains, but any subsequent instances are given an "_rnm#" suffix, where "#" is an index beginning with 0 (and increasing as more instances are found).
To avoid this warning and subsequent renaming, be sure to give all your signals unique names that differ by more than capitalization.