AR# 14288

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XST - "WARNING:Xst:653 - Signal <my_sig> is used but never assigned. Tied to value 0."

Description

Keywords: synthesis, synthesize

Urgency: Standard

General Description:
When I synthesize a design with XST, the following warning occurs:

"WARNING:Xst:653 - Signal <my_sig> is used but never assigned. Tied to value 0."

What does this mean?

Solution

1

The signal mentioned in this warning has a load, but not a source. This signal and all appropriate following logic will be removed.

To avoid this warning, check your code to ensure that all necessary signal connections are made.

2

XST supports mixed language flows starting with 6.1i. If you have a VHDL port with extended identifiers that is connected to your lower level Verilog module, XST issues the warning message above and does not connect the ports. This is only a problem in mixed language flows. For more information on mixed language flow issues, refer to (Xilinx Answer 16241).
AR# 14288
Date 10/20/2005
Status Active
Type General Article
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