We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 14288

XST - "WARNING:Xst:653 - Signal <my_sig> is used but never assigned. Tied to value 0."


Keywords: synthesis, synthesize

Urgency: Standard

General Description:
When I synthesize a design with XST, the following warning occurs:

"WARNING:Xst:653 - Signal <my_sig> is used but never assigned. Tied to value 0."

What does this mean?



The signal mentioned in this warning has a load, but not a source. This signal and all appropriate following logic will be removed.

To avoid this warning, check your code to ensure that all necessary signal connections are made.


XST supports mixed language flows starting with 6.1i. If you have a VHDL port with extended identifiers that is connected to your lower level Verilog module, XST issues the warning message above and does not connect the ports. This is only a problem in mixed language flows. For more information on mixed language flow issues, refer to (Xilinx Answer 16241).
AR# 14288
Date 10/20/2005
Status Active
Type General Article
Page Bookmarked