General Description: When I run "Synthesize" from Project Navigator with a CORE Generator module, the following XST errors are reported:
"Continuing compilation of source file 'design_top.prj' ERROR:Xst:1031 - inter_blk_rec.v Line 837. Module 'C_MUX_BUS_V5_0' not defined ERROR:Xst:1031 - inter_blk_rec.v Line 1937. Module 'C_REG_FD_V5_0' not defined ERROR:Xst:1076 - top_inter_deinter.v Line 58. Identifier 'INIT' not declared 61 errors in compilation --> EXEWRAP detected a return code of '6' from program 'C:/Xilinx/bin/nt/xst.exe'
Done: failed with exit code: 0006."
The errors above are reported by XST (Xilinx Synthesis Tool) -- other synthesis tool may issue slightly different errors.
These errors may be seen if the following cores are used in your design:
DDC_v1_0 (Verilog or VHDL) MAC_v2_0 (Verilog) SID_v2_0 (Verilog) (SID is also known as Interleaver/Deinterleaver)
The error occurs because the behavior model generated by CORE Generator does not include the "synopsys translate_off", "synopsys translate_on" and "synthesis black_box" attributes.
To work around this problem, manually add "synopsys translate_off", "synopsys translate_on" and "synthesis black_box" to the appropriate places in the behavioral model.
For each behavioral model generated by CORE Generator (edit <my_core>.vhd file), add the following two lines :
-- synopsys translate_off <==== Add this line at the top of the file LIBRARY ieee; USE ieee.std_logic_1164.ALL; ... ... ... END deinter_blk_rec_a; -- synopsys translate_on <==== Add this line at the end of the file
Edit the <my_core>.v file.
There are three modules in each behavioral file: one for the main core module, one for the module "ROC", and another for module "TOC". Therefore, a total of three pairs of "synopsys translate_off" and "synopsys translate_on" attributes must be added. In addition, three "//synthesis black_box" must be added.