Description

General Description:

When I synthesize a VHDL design with XST, the following error occurs:

"ERROR:HDLParsers:1202 - <file>.vhd Line xx. Redeclaration of symbol <inst>."

Solution

The name of each lower-level instance of hierarchy, primitives, or black boxes must be unique. Repeating an instance name causes this error.

To avoid this error, assign a unique name to each instantiation instance in your design.

XST does not allow the instance name of an instantiation to match the name of the component itself. For example, the following instantiation flags an error:

lower: lower port map (a, b, c);

Change the instance name to a unique name, such as:

lower_inst: lower port map (a, b, c);