.vhd Line xx. Redeclaration of symbol UPGRADE YOUR BROWSER We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
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Safari. Thank you! General Description: When I synthesize a VHDL design with XST, the following error occurs: "ERROR:HDLParsers:1202 - <file>.vhd Line xx. Redeclaration of symbol <inst>." The name of each lower-level instance of hierarchy, primitives, or black boxes must be unique. Repeating an instance name causes this error. To avoid this error, assign a unique name to each instantiation instance in your design. XST does not allow the instance name of an instantiation to match the name of the component itself. For example, the following instantiation flags an error: lower: lower port map (a, b, c); Change the instance name to a unique name, such as: lower_inst: lower port map (a, b, c);AR# 14370
XST - "ERROR:HDLParsers:1202 -
Description
Solution
AR# 14370
Date
12/15/2012
Status
Active
Type
General Article