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AR# 14373

4.2i CORE Generator - Simulation error: "/test/sid_v2/beh/inter_blk_rec.v(179): Instantiation of 'glbl' failed (design unit not found)..."

Description

Keywords: COREGen, core, ModelSim, tech, simulator, Verilog, behavioral, simulation, glbl.v, glbl, MTI

Urgency: Standard

General Description
When I simulate a design with Core modules, an error reports that the instantiation of "glbl" failed and that the module is not found.

For example, the ModelSim simulator issues the following error:

"# ERROR: /home/michie/coregen/test/sid_v2/beh/inter_blk_rec.v(179): Instantiation of 'glbl' failed (design unit not found).
# Region: /test/uut/u1_int
# Searched libraries:
# /group/techsup/data/mti/5.5d_4.2i_eip2.18/xilinxcorelib_ver
# /group/techsup/data/mti/5.5d_4.2i_eip2.18/unisims_ver
# work"

Solution

For certain cores such as:

MAC v2_0
DDC v1_0
SID v2_0 (Interleaver/Deinterleaver)

CORE Generator will generate Verilog behavioral models (<core_name>.v) with global signals such as GSR and GTS. These signals are defined in the "glbl.v" file which is located in $XILINX/verilog/src/.

It is necessary to compile this module with the other design files and load it along with the "toplevel.v" file or the "testbench.v" file for simulation.
AR# 14373
Date Created 03/29/2002
Last Updated 10/08/2003
Status Archive
Type General Article