We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 14388

4.2i Virtex-E PAR - Clock net routing for signals that have the "USELOWSKEWLINES" constraint applied to them is inconsistent


Keywords: backbone, low skew, USELOWSKEWLINES, routed

Urgency: Standard

General Description:
Signals that have the "USELOWSKEWLINES" constraint applied to them are not routed as expected.

In some cases, the problem was related to the fact that more signals were assigned a USELOWSKEWLINES constraint than the number of backbone resources available. In another case, a clock signal incorrectly used multiple backbone resources.


This problem is fixed in the latest 4.2i Service Pack available at:
The first service pack containing the fix is 4.2i Service Pack 2.

The new router improvements include new clock-routing templates and the following new routing priorities:

1. If USELOWSKEWLINES is applied to a clock net for Virtex/E, the backbone will be used regardless of the incurred delay.

2. Signals with the USELOWSKEWLINES constraint will be routed with one backbone resource per signal.

3. If there are more signals with USELOWSKEWLINES constraints than backbone resources available, a low-skew template will be used for some that do not use a backbone resource.

4. If there are clock signals that do not have a USELOWSKEWLINES constraint and backbone resources are available, as many as possible will be upgraded to use the backbone resources.

5. If there are clock signals without USELOWSKEWLINES constraints and no backbone resources are available, the signals will be routed using a low-skew template appropriate to the shape of the net.

While the new routing templates and priorities are not expected to cause any problems for designs that were routing successfully, you may revert to the prior 4.2isp1 behavior by setting the following environment variable:



(NOTE: This answer record applies only to Virtex, Virtex-E and Spartan-II architectures. These changes have no effect on Virtex-II clock routing.)
AR# 14388
Date 10/23/2008
Status Archive
Type General Article