AR# 14424

11.1 Timing Analyzer/NGDANNO - DDR clock-to-out times in timing simulation do not match Timing Analyzer

Description

DDR clock-to-out times in timing simulation do not match those in Timing Analyzer/TRACE. There is approximately a 400 ps difference between the timing report and the timing simulation when DDR output flip-flops are used. 

 

Which number is correct? How can I fix this?

Solution

The timing reported by the Timing Analyzer and TRACE static timing analysis tools is correct.

AR# 14424
Date 05/14/2014
Status Archive
Type General Article